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AR# 12097

4.1i CORE Generator - Cores introduced in 3.1i IP Update #4 (D_IP4) cannot be regenerated; a "<core> not found" error is issued

Description

Keywords: CORE Generator, COREGen, D_IP4, E_IP1

Urgency: Hot

General Description:
If a 3.1i design contains any of the cores listed below (introduced in 3.1i IP update #4), and an attempt is made to regenerate these particular cores, a "<core> not found" error may be reported.

Cores and specific versions introduced in 3.1i IP Update #4, (also known as D_IP4) that are not on the 4.1i CD are listed below:

(If you are unsure which version of the core you have used in your 3.1i design, check this by opening the <core_name>.xco file using any text editor. XCO files are generated each time you generate the core.)

blkmemsp_v3_2.........................(Block Memory Single Port)
blkmemdp_v3_2.........................(Block Memory Dual Port)
lfsr_v1_0.....................................(Linear Feedback Shift Register)
dds_v3_1....................................(Direct Digital Synthesizer)
da_dct_v1_0...............................(Discrete Cosine Transform)

and the following paid cores:

convolution_encoder_v1_0........(Convolution Encoder, paid core)
rs_decoder_v2_0........................(Reed-Solomon Decoder, paid core)
rs_encoder_v2_0........................(Reed-Solomon Encoder, paid core)
sid_v1_0.....................................(Interleaver-Deinterleaver, paid core)

NOTE: As the IP updates are cumulative, you may find older core versions in the D_IP4 update file (i.e., you will see D_IP1, D_IP2, and D_IP3 cores in the D_IP4 update). These cores are not affected by this problem.

For example, the Block Memory core, v3_1, and earlier versions are not affected by this issue -- only v3_2 is.

Also, this problem only applies to customers who are still in the early phases of their designs, when it is more likely that they will try to:

1. Regenerate one of the above cores;
2. Perform functional simulation of the design through FISE Project Navigator;
3. Re-synthesize the design through FISE Project Navigator.

If you try to perform any of the above operations, an error similar to the following will be reported:

"lfsr_v1_0 not found"

For 3.1i designs that contain the listed cores, but do not require regeneration of the cores, functional simulation or re-synthesis are not affected by this problem; you should be able to process your design through the other implementation steps using the 4.1i software. As long as you have already generated the necessary EDIF netlist, the 4.1i software can be used to place and route an already-generated, D_IP4-specific core.

Solution

If you need to regenerate the core, run functional simulation or re-synthesize the design with the above cores; you must then install 4.1i IP Update #1 (E_IP1), which is available at: http://support.xilinx.com/ipcenter/coregen/updates.htm
AR# 12097
Date Created 07/26/2001
Last Updated 09/11/2003
Status Archive
Type General Article