UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 12179

4.1i NGD2VHDL, SIMPRIM - Simulation error: "<Testcase> has OPEN for inputs." (VHDL)

Description

Keywords:NGD2VHDL, NGDBuild, SimPrim, simulation, open, VHDL, inputs, error

Urgency: Standard

General Description:
During Post-NGDBUILD simulation of VHDL designs, the following error is reported:

"<Design_Name> has OPEN for inputs."

Solution

In VHDL, the keyword "OPEN" can be applied to outputs only. If this keyword is applied to INPUT ports, this error will occur.

To work around this, either edit the VHDL code to comply with the language standard, or run Post-PAR simulation instead.
AR# 12179
Date Created 08/29/2007
Last Updated 08/15/2003
Status Archive
Type ??????