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AR# 12191

4.1i Virtex/Virtex-II MAP - Unrelated merging during MAP can lead to poor placement, causing long routing delays

Description

Keywords: placement, placed, bad, poor, delay, range, area_group, unrelated, merge

Urgency: Standard

General Description:
For designs with high slice utilization, a large amount of "unrelated merging" may occur. (Unrelated merging is when MAP has combined logic into the same slice that has no shared pin connectivity.) The MAP report device summary contains a listing of the number and percentage of slices that contain unrelated logic.

Slices containing unrelated logic can cause problems during placement because there may be conflicting placement needs such that there is no satisfactory location for all paths involved. The result is long routing delays for one of the paths.

Solution

For critical logic, it is possible to define a subset of the design as an area group; you can apply a pack factor of 0 to the area group to prevent any unrelated merges from affecting that logic.

INST ABC AREA_GROUP = XYZ;
INST DEF AREA_GROUP = XYZ;
...
AREA_GROUP XYZ RANGE = CLB_Rm1Cn1:CLB_Rm2Cn2 ; (Virtex)

or

AREA_GROUP XYZ RANGE = SLICE_Xm1Yn1:Xm2Yn2 ; (Virtex-II)
AREA_GROUP XYZ COMPRESSION=0;

Applying these constraints to all critical logic ensures that any unrelated merges required to fit the device will occur in non-critical logic.
AR# 12191
Date Created 07/30/2001
Last Updated 08/20/2003
Status Archive
Type General Article