We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

Page Bookmarked

AR# 122

XC3000/XC4000: Using latches in 3k and 4k designs



Cautions When Using Latches 3000 and 4000 Designs
Caution must be exercised when using latches from the 3K and
4K libraries because they are built out of combinatorial logic,
and use a feedback path which is routing dependent. The only exceptions
to this are the latches that exist in the IOBs, which are 'true'
latches. The implications of this are:

- The latch has a nonzero hold time which is routing-dependent
because of the routing-dependent feedback loop.

- If you perform any automatic optimization on your design, the
result can vary widely, from something that works exactly like the
input design, to a design which does not work at all. The actual
result will depend on the logic around the latches and the location
at which the optimization algorithm breaks the feedback loop to
perform optimization.

The most worrisome result of optimization is the design which
appears to work, but is marginal in reality.

- The design will be unacceptable for conversion to hardwire.

Xilinx discourages the use of latches in 3000 and 4000 designs
for the above reasons; however, if you must use them, please be aware
of the implications.


You can make a CLB LATCH in the xc4000 architecture, that is not routing dependent, with a RAM16X1. Tie the address lines to ground, and you now have a level sensitive Gated D-Latch without the use of feedback routing.
AR# 122
Date 10/01/2008
Status Archive
Type General Article