When I attempt to implement a design result, a warning message similar to the following is reported:
"WARNING:CPLD:939 - Unable to map all desired signals into FB10 because too many inputs (>36) are required. Buffering output signal ldata<9> to allow all signals assigned to this function block to be placed."
What does this mean?
In most cases, there are either not enough function block inputs or not enough product terms to fit the equation into the intended macrocell. As a result, the fitter places the logic in a different macrocell, and it then routes the output (the result) to the intended macrocell. This uses only one function block input and one product term in the original macrocell. This results in an additional level of logic delay. If your design can tolerate this delay, then this warning can be safely ignored.
denable <= a or b or c; // mapped to pin XX, macrocell YY function block ZZ
denable <= d_buff; // mapped to pin XX, macrocell YY function block ZZ
d_buff <= a or b or c; // mapped to a function block other than ZZ
In many cases, this buffering can be avoided if the pin is moved to a different function block. If the additional timing adder is not acceptable and the pin cannot be moved, this might be solved by moving other pin-assigned outputs (moving inputs will not help) in that function block (ZZ). If no pins are movable, you can use the MAXPT constraint to force the tools to buffer a different equation. For more details on the MAXPT constraint, see (Xilinx Answer 17293).