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AR# 12249

4.1i CPLD - ABEL test vector timing simulation fails

Description

Keywords: CPLD, ABEL, timing simulation, test vectors

Urgency: Standard

General Description:
The first test vector executes while the reset pulse is still initializing the user registers; therefore, the expected results from the first clock pulse are not correct.

This only happens for ABEL test vectors converted to a testbench, and only during timing simulation.

Solution

You can work around this by inserting a "dummy" vector as your first ABEL test vector.

This problem is fixed in the latest 4.1i Service Pack, available at:
http://support.xilinx.com/support/techsup/sw_updates.
The first service pack containing the fix is 4.1i Service Pack 1.

AR# 12249
Date Created 08/02/2001
Last Updated 08/05/2003
Status Archive
Type General Article