2. Support
  3. AR# 1225: How to re-target a different Xilinx device family with Viewlogic's Altran
  4. AR# 12251: 4.1i Project Navigator - Unable to select post-route EDIF/VHDL/Verilog (timing) simulation netlist

AR# 12251

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4.1i Project Navigator - Unable to select post-route EDIF/VHDL/Verilog (timing) simulation netlist

Description

Keywords: 4.1i, Project Navigator, EDIF, netlist

Urgency: Standard

General Description:
When using the EDIF flow, I am unable to create a post-route EDIF/VHDL/Verilog (timing) simulation netlist.

Solution

This can be done by running NGD2VHDL, NGD2EDIF, or NGD2VER from the command line. Please see the Development System Reference Guide for details on how to do this for each individual program.

This problem is fixed in the latest 4.1i Service Pack, available at:
http://support.xilinx.com/support/techsup/sw_updates
The first service pack containing the fix is 4.1i Service Pack 2.
AR# 12251
Date 08/05/2003
Status Archive
Type General Article
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