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AR# 12290

3.1i CORE Generator - Dual-Port Block Memory simulation warning: "Design error: out of range memory select on pipelinea...."

Description

Keywords: CORE Generator, COREGen, dual, port, block, memory, design error, out, range, pipelinea, Verilog, behavioral, simulation, XilinxCoreLib

Urgency: Standard

General Description:
When I simulate a design with CORE Generator Dual-Port Block Memory, the simulator reports the following message:

WARNING [STX-RNGDEF]:
/nfs/ibu_apps/xilinx/E.30/verilog/src/XilinxCoreLib/BLKMEM-
DP_V3_0.v, line 783: module BLKMEMDP_V3_0, instance
ao16f_fifo32x32_1rs_1w.uMEM.inst, Design Error: Out of range
memory select on pipelinea. [1] is selected, but only [0:0] is defined.

Solution

The problem is in Verilog behavioral model "blkmemdp_v3_2.v" and earlier versions of the "dp blk" memory. This problem will be fixed in
Dual-Port Block Memory v4_0, which is scheduled to be released in the E_IP1 update in late October, 2001.

If a fix for this is needed before the E_IP1 release, please contact Xilinx Technical Support at:
http://support.xilinx.com/support/clearexpress/websupport.htm
Please mention this Answer Record number (#12290) when you create your WebCase.
AR# 12290
Date Created 08/08/2001
Last Updated 08/23/2002
Status Archive
Type General Article