We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 12293

12.1 Constraints - How do I create register (flip-flop) initialization values (set/reset)?


How do I set register (flip-flop) initialization values (set/reset)?


Use the INIT attribute to control the initial value of the registers during device power-up. Use the "S" value to set on power-up, and the "R" value to reset on power-up. (The default is "reset".)

You can apply the INIT attribute directly to a register instantiation in Verilog/VHDL, or you can declare it in the UCF for the register instance name. If the register logic is inferred, the reset logic must be coded into the design.

Use the following for coding the INIT attribute for inferred and instantiated logic.

For XST Synthesis

"Test" is the top-level file with XST attributes that, at power on, includes the following:
- One inferred register that is preset (outa)
- One inferred register that is reset (outb)
- One instantiated register that is preset (FD0)
- One instantiated register that is reset (FD1)

module test (clk, ina, inb, rst, D_IN, Q_OUT, outa, outb);

input clk, ina, inb, rst;
input [1:0] D_IN;
output [1:0] Q_OUT;
output outa, outb;

reg outa;
reg outb;
wire re;

// Initialized Preset-FF (outa) and Reset-FF (outb)
ROCBUF u1 (.I(rst), .O(re));
//synthesis attribute box_type of ROCBUF is "black_box"

always @ (posedge clk or posedge re) begin
if (re) begin
outa = 1'b1;
outb = 1'b0;
outa = ina;
outb = inb;

// Initialized preset flip-flop for XST
FD FD0 (.Q (Q_OUT[0]), .D (D_IN[0]), .C (clk));
// synthesis attribute INIT of FD0 is "R"

// Initialized reset flip-flop for XST
FD FD1 (.Q (Q_OUT[1]), .D (D_IN[1]), .C (clk));
// synthesis attribute INIT of FD1 is "S"


module ROCBUF (I, O);
input I;
output O;

In the UCF, you can apply the INIT attribute to a register instance that is inferred or instantiated in your HDL design (if the instance name is known), as follows:

AR# 12293
Date 12/15/2012
Status Active
Type General Article
  • ISE - 10.1
  • ISE Design Suite - 11.1
  • ISE Design Suite - 11.2
  • More
  • ISE Design Suite - 11.3
  • ISE Design Suite - 11.4
  • ISE Design Suite - 11.5
  • ISE Design Suite - 12.1
  • ISE Design Suite - 12.2
  • Less
Page Bookmarked