AR# 12293: 12.1 Constraints - How do I create register (flip-flop) initialization values (set/reset)?
AR# 12293
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12.1 Constraints - How do I create register (flip-flop) initialization values (set/reset)?
Description
How do I set register (flip-flop) initialization values (set/reset)?
Solution
Use the INIT attribute to control the initial value of the registers during device power-up. Use the "S" value to set on power-up, and the "R" value to reset on power-up. (The default is "reset".)
You can apply the INIT attribute directly to a register instantiation in Verilog/VHDL, or you can declare it in the UCF for the register instance name. If the register logic is inferred, the reset logic must be coded into the design.
Use the following for coding the INIT attribute for inferred and instantiated logic.
For XST Synthesis
"Test" is the top-level file with XST attributes that, at power on, includes the following: - One inferred register that is preset (outa) - One inferred register that is reset (outb) - One instantiated register that is preset (FD0) - One instantiated register that is reset (FD1)
module test (clk, ina, inb, rst, D_IN, Q_OUT, outa, outb);
In the UCF, you can apply the INIT attribute to a register instance that is inferred or instantiated in your HDL design (if the instance name is known), as follows: