We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 12301

5.1i Timing Analyzer/TRCE (Trace) - The TIG constraint is not properly applied to the design


General Description:

My FROM:TO TIG constraint is not being properly applied to my design. Why is this happening?


This problem is caused by path intersections between multiple TIGs.

To work around this issue, combine all TIGs that have common destination groups. This will produce the correct behavior.

For more information, please see (Xilinx Answer 9297).

AR# 12301
Date 01/18/2010
Status Archive
Type General Article
Page Bookmarked