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AR# 12378

Virtex-II/Pro - What happens to the Phase Shifted output of a DCM when it reaches the maximum value of 255 or the end of the delay line?

Description

Keyword: Virtex-II, phase, shift, DCM, counter, overflow, pro

What happens to the Phase Shifted output in a DCM when it reaches the maximum value of 255 or the end of the delay line? What does the Phase Shift counter in a DCM exhibit when it reaches 255 (the max value)?

Solution

When the DCM is incremented/decremented beyond 255 (or -255), there is no delay line change and a phase change does not occur. The phase shift value remains at +255 (-255), and the "DPS Overflow" signal (STATUS[0]) goes High. When a change to the PS value occurs in the opposite direction, the "DPS Overflow" signal goes back to Low.

If the phase shift does not reach 255 (-255), but the phase shift has exceeded the delay line range, a phase change will not occur. The phase shift value continues to increment or decrement unless +/-255 is reached by the phase shift counter (see above). The "DPS Overflow" signal (STATUS[0]) goes High. When a change to the PS value occurs in the opposite direction and the phase shift value is incremented or decremented back to a value that corresponds to a valid absolute delay in the delay line, the "DPS Overflow" signal goes back to Low.

When the phase shift reaches 255 (-255), the phase shift counter stays at its maximum value of 255 until it is set to decrement. Status[0] indicates when the counter has exceeded its maximum value.

NOTES:

1. The delay line range is specified by the FINE_SHIFT_RANGE value described in the "Module 3: DC and Switching Characteristics" section of the Virtex-II and Virtex-II Pro data sheets (see links below).

2. In the Virtex-II and Virtex-II Pro User Guides, refer to the Design Considerations -> Digital Clock Managers (DCM) sections for more information on how the FINE_SHIFT_RANGE value limits variable and fixed phase shift.

3. The actual delay line may be longer than the FINE_SHIFT_RANGE. However, only delays up to the FINE_SHIFT_RANGE (with respect to the phase shift mode selected) are guaranteed. You should design with this range in mind and use the STATUS(0) value to indicate maximum phase shift.

The Virtex-II Pro Data Sheet is located at:

http://www.xilinx.com/support/documentation/data_sheets/ds083.pdf
The Virtex-II Pro and Virtex-II Pro X FPGA User Guide is located at:

http://www.xilinx.com/support/documentation/user_guides/ug012.pdf

The Virtex-II FPGA Data Sheet is located at:

http://www.xilinx.com/support/documentation/data_sheets/ds031.pdf
The Virtex-II Platform FPGA User Guide is located at:

http://www.xilinx.com/support/documentation/user_guides/ug002.pdf

AR# 12378
Date Created 08/29/2007
Last Updated 12/15/2012
Status Active
Type General Article