We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 12431

4.1i E_IP1 Core Generator Reed Solomon v2.0 - Setup violations and wrong simulation results in 4k/spartan families


Keywords: RS, FEC, Forward, Error Correction

Urgency: Standard

General Description:

When using NGDANNO and LOGICAL simulations using an SDF file,
simulation will issue "setup violation" warnings and not function correctly.
I am target a 4K or Spartan architecture.


This is due to a timing error that is produced in the SDF file. The problem
only occurs with the 4K/Spartan families. The work around is to:

1. Implement LOGICAL simulations without the SDF file.

2. Implement PHYSICAL simulations instead of LOGICAL. (PHYSICAL
simulations work fine with or without SDF files).

Logical Simulation - NGM file used in NGDAnno
Physical Simulation - NGM is not used in NGDAnno
AR# 12431
Date 05/13/2009
Status Archive
Type General Article