AR# 12461: EXEMPLAR - How do I use new a I/O Buffer that is not in the Leonardo library?
AR# 12461
EXEMPLAR - How do I use new a I/O Buffer that is not in the Leonardo library?
Description
Keywords: primitive, IBUF, OBUF, I/O, pad, nopad
Urgency: Standard
General Description: When Xilinx introduces a new I/O buffer, the buffer may not become available in the Leonardo library until a subsequent release. However, designers can still use this I/O buffer.
The following Verilog and VHDL test cases illustrate how to pass an attribute that tells Leonardo Spectrum to turn off I/O insertion.
Solution
1
Verilog Example
module IBUF_PCIX (O, I); output O; input I;
endmodule
module OBUF_PCIX (O, I); output O; input I;
endmodule
module test (in, out, clk); input pci_in, clk; output pci_out;
reg out; reg obuf_in;
wire ibuf_out;
IBUF_PCIX U_pcix_ibuf (.O(ibuf_out), .I(in));
always @(posedge clk) obuf_in = ibuf_out;
OBUF_PCIX U_pcix_obuf (.O(out), .I(obuf_in));
// special NOPAD attribute to ignore default IO buffering. // exemplar attribute pci_in NOPAD true // exemplar attribute pci_out NOPAD true endmodule // test
2
VHDL Example
library ieee; use ieee.std_logic_1164.all;
entity test is
port ( pci_in : in std_logic; pci_out : out std_logic; clk : in std_logic);
-- special NOPAD attribute to ignore default IO buffering. attribute NOPAD : boolean; attribute NOPAD of pci_in : signal is TRUE; attribute NOPAD of pci_out : signal is TRUE;
end test;
architecture behav of test is component IBUF_PCIX port ( O : out std_logic; I : in std_logic); end component;
component OBUF_PCIX port ( O : out std_logic; I : in std_logic); end component;
signal ibuf_out, obuf_in : std_logic; begin -- behav
U_pcix_ibuf : IBUF_PCIX port map ( I => input, O => ibuf_out);
process (clk) begin -- process if clk'event and clk = '1' then -- rising clock edge obuf_in <= ibuf_out; end if; end process;
U_pcix_obuf : OBUF_PCIX port map ( I => obuf_in, O => output); end behav;