We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

Page Bookmarked

AR# 12467

4.1i SimPrims - Incorrect results are reported when a back-annotated simulation is performed with Block Memory primitives.


Keywords: CORE Generator, COREGen, dual, single, port, block memory, simulation, SimPrim, Asynchronous FIFO.

Urgency: Hot

General Description
When I perform a back-annotated simulation (post-NGDBuild, post-MAP, and timing), incorrect simulation results are reported when my design uses one of the following primitives:

1. ramb16_s9_s9
2. ramb16_s9_s18
3. ramb16_s9_s36

Many CORE Generator cores (such as Block Memory Cores, Asynchronous FIFO, Synchronous FIFO, Sine Cosine, Direct Digital Synthesizer, Pos Phy L4, Pos Phy L3, and FlexBus 4) may use the Block Memory primitives listed above. To see if your design is using these primitives, please use a text editor to open your top-level design EDIF netlist and/or CORE-generated EDIF netlist, and search for any of the primitives listed above.


This problem is fixed in the latest 4.1i Service Pack, available at:
The first service pack containing the fix is 4.1i Service Pack 2.
AR# 12467
Date 08/26/2003
Status Archive
Type ??????