General Description: This Answer Record contains the known issues that are addressed in 4.1i_ip_update1 (also referred to as "E_IP1").
- Virtex-II Pro and Spartan-IIE device support have been added to the E_IP1 update. (Implementation of designs for these two device families will become available in a future software update.) - Version information has been added to the customization GUI of each core. - The IP Capture Tool is introduced in the E_IP1 update. - The CORE Generator Updates Installer Tool is introduced in the E_IP1 update.
Documentation for the IP Capture Tool and Updates Installer are available in the CORE Generator Help menu (main GUI), under "Online Documentation".
GENERAL KNOWN ISSUES
The E_IP1 IP update is only compatible with Xilinx CORE Generator v4.1i, which is included with the ISE v4.1i software. This IP update should not be used with any other versions of CORE Generator (such as v3.1i or earlier).
If Acrobat Reader is not installed, you may not be able to open CORE Generator in Windows 98. For further information, please see (Xilinx Answer 12647).
If you use a Windows 2000 platform, it is recommended that you use the "High Color" setting for your Display. For further information, please see (Xilinx Answer 12372).
Xilinx Implementation Software Issues
1. When importing a deisgn from 3.1i, "Port mis-match " and "unconnected ports" appear during simulation and imlemenation. Please see (Xilinx Answer 13062)
2. Virtex-II designs fail with the following error message from MAP: "FATAL_ERROR:Pack:pktv2rpmutil.c:184.108.40.206.1 - Exceeded the max number of shapes in an RMP." Please see (Xilinx Answer #12463).
3. Virtex-II Pro designs may with following error message from MAP: "ERROR:Pack:1052 - The RLOC value of X36Y123 on component N11246 in RPM hset does not resolve to a legal site in this device." This problem is encountered when the NCD is generated; it is a MAP issue, and it will addressed in 4.1i Service Pack 2, which was released in October, 2001.
4. When a back-annotated simulation is performed with Block Memory primitives, incorrect simulation results are given. Please see (Xilinx Answer 12467).
IP Capture Tool
If you are planning on using IP Capture Tool introduced in E_IP1, please read (Xilinx Answer 12862) for information on "IP Capture Tool Known Issues for E_IP1" before using the tool.
The EDIF file generated is incomplete when certain "Limit Data Pitch" option and "Select Primitive" are used. Please see (Xilinx Answer 12673).
Simulation Known Issues
1. When VHDL behavioral simulation models for Virtex-II Block Memories (blkmemv2dp_v2_0.vhd and blkmemv2sp_v2_0.vhd) are compiled, the VHDL -93 Compliancy switch must be used. Please consider using the latest version of the core. Contact www.xilinx.com to get help on obtaining the latest software.
2. When XilinxCoreLib files are compiled using Synopsys VSS or VCSi, simulators may report a number of warnings and errors. Please see (Xilinx Answer 12630).