We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 12485

4.1i Virtex-II PAR - Placer crashes after "Starting Clock Logic Placement."


Keywords: PAR, place placer, clock, logic, placement, crash

Urgency: Hot

General Description:
The placer crashes after "Starting Clock Logic Placement".


The problem occurs because the slave-I/O of an LVDS-pair was locked and the corresponding master was unlocked.

This problem will be fixed in the next major software release after 4.1i.

Meanwhile, work around this problem by either locking both I/Os in the pair, or not locking either.
AR# 12485
Date 10/23/2008
Status Archive
Type General Article
Page Bookmarked