AR# 12506: EXEMPLAR - How do I implement differential signaling (LVDS, LVPECL, etc) for a Virtex-II?
AR# 12506
EXEMPLAR - How do I implement differential signaling (LVDS, LVPECL, etc) for a Virtex-II?
Description
Keywords: LVDS, LVPECL, Virtex-II, IOSTANDARD
Urgency: Standard
General Description: How do I implement differential signaling for a Virtex-II device?
NOTE: Leonardo Spectrum's PAD attribute cannot be used to pass the constraint.
Solution
1
Below is some very simple VHDL that demonstrates the instantiation of the OBUFDS component with the IOSTANDARD attribute being passed on to the instantiated OBUFDS:
library IEEE; use IEEE.STD_LOGIC_1164.ALL;
entity differential_signaling is Port(d0 : in std_logic; --data in to obufds d1 : in std_logic; --data in to obufds d0_out : out std_logic; d0_out_ob : out std_logic; d1_out_ob : out std_logic; d1_out : out std_logic); end differential_signaling;
architecture differential_signaling_arch of differential_signaling is
component OBUFDS port(I : in std_logic; O : out std_logic; OB : out std_logic); end component;
attribute IOSTANDARD : string; attribute IOSTANDARD of U0 : label is "LVDS_25"; attribute IOSTANDARD of U1 : label is "LVDS_25";
begin
U0: OBUFDS port map (I => d0, O => d0_out, OB => d0_out_ob);
U1: OBUFDS port map (I => d1, O => d1_out, OB => d1_out_ob); end architecture;
Below is some very simple Verilog that demonstrates the instantiation of the OBUFDS component with the IOSTANDARD attribute being passed on to the instantiated OBUFDS: