AR# 12507

|

3.x FPGA Express - How do I implement differential signaling (LVDS, LVPECL, etc) for a Virtex-II?

Description

Keywords: LVDS, LVPECL, Virtex-II, IOSTANDARD

Urgency: Standard

General Description:
How do I implement differential signaling for a Virtex-II device?

Solution

1

The simple VHDL below demonstrates the instantiation of an OBUFDS component, with the IOSTANDARD attribute being passed on to the instantiated OBUFDS:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity differential_signaling is
Port(d0 : in std_logic; --data in to obufds
d1 : in std_logic; --data in to obufds
d0_out : out std_logic;
d0_out_ob : out std_logic;
d1_out_ob : out std_logic;
d1_out : out std_logic);
end differential_signaling;

architecture differential_signaling_arch of differential_signaling is

component OBUFDS
port(I : in std_logic;
O : out std_logic;
OB : out std_logic);
end component;

attribute IOSTANDARD : string;
attribute IOSTANDARD of U0 : label is "LVDS_25";
attribute IOSTANDARD of U1 : label is "LVDS_25";

begin

U0: OBUFDS
port map (I => d0,
O => d0_out,
OB => d0_out_ob);

U1: OBUFDS
port map (I => d1,
O => d1_out,
OB => d1_out_ob);
end architecture;

2

The simple Verilog below demonstrates the instantiation of an OBUFDS component, with the IOSTANDARD attribute being passed on to the instantiated OBUFDS:

module differential_signaling (d0, d1, d0_out, d0_out_ob, d1_out, d1_out_ob);

input d0 ; //-data in to LVPECL output
input d1 ; //--data in to LVPECL output
output d0_out ;
output d0_out_ob ;
output d1_out_ob ;
output d1_out ;

OBUFDS U0 (.I ( d0), .O ( d0_out), .OB ( d0_out_ob)); //synopsys attribute IOSTANDARD "LVDS_25"
OBUFDS U1 (.I ( d1), .O ( d1_out), .OB ( d1_out_ob)); //synopsys attribute IOSTANDARD "LVDS_25"

endmodule
AR# 12507
Date 08/11/2003
Status Archive
Type General Article
People Also Viewed