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AR# 12516

4.1i CPLD XPLA3 Hprep6 - The JEDEC produced from the Xilinx software does not disable the ISP pins (JTAG)

Description

Keywords: 4.1i, XPLA3, ISP, JEDEC

Urgency: Hot

General Description:
The JEDEC produced from the 4.1i Xilinx software does not disable the ISP pins, leaving them dedicated to JTAG functionality; this occurs regardless of the setting in the ISE GUI. The report file does show that the setting for "Reserve JTAG Port Pins" was read in properly.

Solution

This is fixed in the latest 4.1i Service Pack, available at:
http://support.xilinx.com/support/techsup/sw_updates/
The first version of software to contain this fix is 4.1i Service Pack 2.
AR# 12516
Date Created 09/10/2001
Last Updated 08/05/2003
Status Archive
Type General Article