General Description: Depending upon the description in the resolutions below, the following errors occur:
"INTERNAL_ERROR:Xst:cmain.c:3004:1.63 - To resolve this error, please consult the Answers Database and other online resources at http://support.xilinx.com"
"FATAL_ERROR:Xst:Portability/export/Port_Main.h:116:1.9 - This application has discovered an exceptional condition from which it cannot recover. Process will terminate. To resolve this error, please consult the Answers Database and other online resources at http://support.xilinx.com"
Many of the problems discussed in this Answer Record were resolved in the 5.1i version of XST.
Solution
1
A constant declared in the declarative section of a process has been known to cause these errors. To avoid the problem, declare the constant outside of the process.
For example:
: : process (clk, reset) constant static_value : std_logic_vector (2 downto 0) := "001"; begin : :
should be:
<architecture_declaration> : constant static_value : std_logic_vector (2 downto 0) := "001"; begin : : process (clk, reset) begin : :
2
State machines can also cause the above errors. The only way to work around the problems in this case is to disable the FSM Encoding style:
ISE GUI:
1. Within the Process View box, right-click on "Synthesize". 2. Select the HDL Options tab. 3. Change the "FSM Encoding Algorithm" to "None".
XST Command Line:
1. Change "-fsm_encoding Auto" to "-fsm_encoding None".
3
For VHDL projects, you can work around the problem by moving packages from the work library to a user-defined library.
4
The error messages above can also occur when an array of ports is left unconnected. Connecting the ports successfully resolves the problem.
5
The slice-packing feature has also been known to cause the above errors. The following is a definition of slice-packing for XST:
The Slice Packing (SLICE_PACKING) option enables the XST internal packer; the XST internal packer packs the output of global optimization in the slices. The packer attempts to pack critical LUT-to-LUT connections within a slice or a CLB, exploiting the fast feedback connections among LUTs in a CLB. Please see the "SLICE_PACKING" section in the Constraints Guide for details.
To turn off slice packing, follow these steps:
ISE GUI:
1. Within the Process View box, right-click on "Synthesize". 2. Select the Xilinx Specific Options tab. 3. Deselect the "Slice Packing" option.
XST Command Line:
1. Change "-slice_packing YES" to "-slice_packing NO".
6
There appears to be a Window NT OS dependency with this error. If you have attempted all previous solutions, try running the software tools on Windows 2000 or UNIX.
7
Another way to work around this issue is to use wild cards in a case statement. Below is the unmodified and modified Verilog code:
Example of unmodified code:
: : case (protocol)
2'b1? : begin // moto cs high...
hcsn <= 1'b1; hrdn <= 1'b1; hwrn <= 1'b0;
end
default : begin
hcsn <= 1'b0;
end
endcase : :
Example of modified code:
: : casez (protocol) // changed from case to casez
2'b1? : begin // moto cs high...
hcsn <= 1'b1; hrdn <= 1'b1; hwrn <= 1'b0;
end
default : begin
hcsn <= 1'b0;
end
endcase : :
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AR# 12545
Date
08/06/2003
Status
Archive
Type
General Article
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