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AR# 12552

4.1i UniSim - When I simulate a Block RAM with UniSim, PORT A does not function correctly

Description

Keywords: ModelSim, MXE, Port, A, UniSim, VHDL, Block, RAM

Urgency: Standard

General Description:
When I simulate a Block RAM with UniSim in dual-port mode, the Block RAM PORT A does not function correctly.

Solution

This problem is fixed in the latest 4.1i Service Pack, available at:
http://support.xilinx.com/support/techsup/sw_updates
The first service pack containing the fix is 4.1i Service Pack 1.
AR# 12552
Date Created 08/29/2007
Last Updated 08/26/2003
Status Archive
Type ??????