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AR# 12596

LogiCORE Direct Digital Synthesis (DDS) and Sine/Cosine LUT v4.0 and 4.1i MAP - Why does MAP fail with "ERROR:Pack:679 - Unable to obey design constraints."?


Keywords: Sine/Cosine, Sine, Cosine, direct digital synthesis

When I generate a Sine/Cosine core and run my design through the Xilinx Implementation Tools, the following MAP error is reported:

"ERROR:Pack:679 - Unable to obey design constraints (MACRONAME=hset, RLOC=X3Y8), which require the combination of the following symbols into a single slice component:

LUT symbol "BU10" (Output Signal = N184)
LUT symbol "BU11" (Output Signal = N185)
MUXF5 symbol "BU12" (Output Signal = N181)
MUXF6 symbol "BU13" (Output Signal = N3)
FLOP symbol "BU184" (Output Signal = INT_SINE<2>)
Unable to pack the register BU184 because of connectivity restrictions.
Please correct the design constraints accordingly."

This only occurs when I use the following parameters:

- Target a Virtex-II or Virtex-II Pro
- Use Distributed Memory
- Register the outputs with a sync or async clear
- Have Theta widths of 6, 7, or 8


When you use the parameters stated above, the core generates relative placement that is invalid; it creates illegal connections that cause MAP errors when MAP pulls the reg into the slice.

To work around this problem, turn off Placement in the CORE Generator GUI when creating the Sine/Cosine or DDS core; this is done by deselecting "Layout: Create RPM".

Please See (Xilinx Answer 30162) for a detailed list of LogiCORE Sine-Cosine Look-Up Table (Sin Cos LUT) Release Notes and Known Issues.
AR# 12596
Date 03/13/2008
Status Archive
Type General Article