AR# 12648: 4.1i XST XC9500 - Using a transparent latch with an asynchronous set leads to incorrect implementation
4.1i XST XC9500 - Using a transparent latch with an asynchronous set leads to incorrect implementation
Keywords: XC9500, XST, latch, asynchronous set
General Description: When using a transparent latch with an asynchronous set, the XST will incorrectly infer the asynchronous set.
Please note: The following only applies to the Xilinx XC9500 family of devices (XC9500/XL/XV).
This is fixed in 4.2i.
To work around this situation in 4.1i, manually instantiate the LDCP component. You may look up the component in the on-line libraries guide to determine port naming. To access the libraries guide, go to http://www.support.xilinx.com/, then select "Software Manuals".
The following is an example of VHDL declaration:
component LDCP port (Pre : in std_logic; D: in std_logic; G: in std_logic; CLR : in std_logic; Q: out std_logic); end component;