General Description: I am generating Single-Port Block Memory v4_0 for Virtex; if I select "Limit Data Pitch" to be 8, with "Select Primitive" set to 256x16, I receive an incomplete EDIF netlist from CORE Generator. CORE Generator displays a message indicating that "the core has been generated successfully." However, if I open the EDIF netlist generated by CORE Generator, I cannot see any RAMB4 or RAMB16 components.
When Single-Port Block Memory v4_0 is generated for Virtex-II, if "Limit Data Pitch" is set to 16, with "Select Primitive" set to 512x32, CORE Generator will generate an incomplete EDIF netlist. (The problem is not obvious unless the generated EDIF netlist is examined carefully or the MAP trimming report is checked.)
If the Single-Port Block Memory is the only module in the design, MAP will report an error similar to the following:
ERROR:Pack:198 - NCD was not produced. All logic was removed from design. This is usually due to having no input or output PAD connections in the design and no nets or symbols marked as 'SAVE'. You can either add PADs or 'SAVE' attributes to the design, or run 'map -u' to disable logic trimming in the mapper. Problem encountered generating the NCD. Mapping completed. See MAP report file "top.mrp" for details.
When Single-Port Block Memory v4_0 is being generated for a Virtex device, and a 256x16 primitive has been selected, the "limit data pitch" option should be disabled during the core generation.
When Single-Port Block Memory v4_0 is being generated for a Virtex-II device, and a 512x32 primitive has been selected, the "limit data pitch" option should be disabled during the core generation.