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AR# 12713

Synopsys Formality/Verplex Conformal - Formal Verification fails while checking the post-PAR design


General Description: 

Formal Verification fails while checking the post-PAR design.


This problem can occur when the "-dp" option has been used in MAP. This option causes a pattern of "LUT driving a flip-flop" to get mapped into unused block RAMs. Since the formal verification tools cannot map the logic inside the block RAM to the RTL netlist, errors will be reported.  


To work around this problem, do not use the "-dp" option in MAP.

AR# 12713
Date 05/14/2014
Status Archive
Type General Article
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