AR# 12718: 4.1i Virtex-II MAP - "FATAL_ERROR:Pack:pksv2slice.c:333:1.16.18.1 - Unable to create route through signal..."
AR# 12718
4.1i Virtex-II MAP - "FATAL_ERROR:Pack:pksv2slice.c:333:1.16.18.1 - Unable to create route through signal..."
Description
Keywords: MAP, Virtex-II, related packing
Urgency: Hot
General Description: MAP fails with the following fatal error during related packing:
"FATAL_ERROR:Pack:pksv2slice.c:333:1.16.18.1 - Unable to create route through signal. Signal Cbout[0]_rt already exists. Process will terminate. To resolve this error, please consult the Answers Database and other online resources at http://support.xilinx.com."
Solution
This problem is a regression from version 3.1i, and the failing circuit can be traced from the signal name in the error message. In all cases investigated so far, this signal is driven by a register and, among other things, drives an inverter that in turn drives a pair of LUT1s.
In turn, the LUT1s each drive a register input and MUXCY select pin. The failure appears to involve MAP merging the inverter and the LUT1s. You may work around the problem by preventing this merger; to do this, apply the following UCF constraint to the signal between the inverter and the LUT1s:
NET "sig_name" KEEP ;
This work-around does not degrade the circuit performance.