AR# 12759: XST - How do I code bidirectional LVDS (BLVDS) buffers in VHDL and Verilog for a Virtex-II device?
AR# 12759
XST - How do I code bidirectional LVDS (BLVDS) buffers in VHDL and Verilog for a Virtex-II device?
Description
General Description:
How do I code bidirectional LVDS buffers in VHDL and Verilog for a Virtex-II device?
The bidirectional LVDS solution in the Virtex-II architecture is identical to the Virtex-E solution. Because LVDS is intended for point-to-point applications, BLVDS (Bus LVDS) is not an IEEE/EIA/TIA standard implementation and requires careful adaptation of I/O and PCB layout design rules. Below are VHDL, Verilog, and UCF examples.
Solution
VHDL
library IEEE;
use IEEE.std_logic_1164.all;
entity LVDS_IOBUFDS is
port (CLK_p, CLK_n, DATA_p, DATA_n, Tin_p, Tin_n: in STD_LOGIC;
IODATA_p, IODATA_n : inout STD_LOGIC;
Q_p, Q_n : out STD_LOGIC);
end LVDS_IOBUFDS;
architecture BEHAV of LVDS_IOBUFDS is
component IBUFDS is
generic (IOSTANDARD : string);
port (I : in STD_LOGIC;
IB: in STD_LOGIC;
O : out STD_LOGIC);
end component;
component OBUFDS is
generic (IOSTANDARD : string);
port (I : in STD_LOGIC;
O : out STD_LOGIC;
OB : out STD_LOGIC);
end component;
component IOBUFDS is
generic (IOSTANDARD : string);
port (I : in STD_LOGIC;
T : in STD_LOGIC;
O : out STD_LOGIC;
IO: inout STD_LOGIC;
IOB: inout STD_LOGIC);
end component;
component IBUFGDS is
generic (IOSTANDARD : string);
port(I : in STD_LOGIC;
IB: in STD_LOGIC;
O : out STD_LOGIC);
end component;
component BUFG is
port(I : in STD_LOGIC;
O : out STD_LOGIC);
end component;
signal datain2 : std_logic;
signal odata_out: std_logic;
signal DATA_int : std_logic;
signal Q_int : std_logic;
signal CLK_int : std_logic;
signal CLK_ibufgout : std_logic;
signal Tin_int : std_logic;
begin
UI1: IBUFDS
generic map (IOSTANDARD => "BLVDS_25")
port map (DATA_p, DATA_n, DATA_int);
UI3: IBUFDS
generic map (IOSTANDARD => "BLVDS_25")
port map (Tin_p, Tin_n, Tin_int);
UO1: OBUFDS
generic map (IOSTANDARD => "BLVDS_25")
port map (Q_int, Q_p, Q_n);
UIO2: IOBUFDS
generic map (IOSTANDARD => "BLVDS_25")
port map (odata_out, Tin_int, datain2, IODATA_p, IODATA_n);