General Description: When instantiating Select I/O buffers, FPGA Express may change the buffer from the standard instantiated to LVTTL. This has occurred with at least the SSTL2 standard. This change generates the following Place and Route error:
"ERROR:Place:1747 - The IOB ddr_ad<8> is locked to site L13 in Bank 3. This violates the Select I/O banking rules."
If you wish to instantiate various Select I/O buffers, the recommended method from the Libraries Guide (Xilinx Manual "Libraries Guide", page 344) is to instantiate the IBUF/OBUF, then to place the appropriate I/O standard on the component. For examples, please refer to (Xilinx Answer 10900).