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AR# 12789

4.i1 ISE - A "jc2_ver" tutorial example contains invalid Verilog syntax

Description

Keywords: JC2_VER, Verilog, syntax, wrong, incorrect

Urgency: Standard

General Description:
The JC2_VER tutorial design contains an initial block that is used to define flip-flop power-up states for functional simulation. The initial assignment for the 4-bit Q output bus is incorrectly written as:

q[3:0] = "0000";

Solution

This does not cause any functional failure, as the default initial state for all flip-flops is zero. However, the valid Verilog assignment should be:

q[3:0] = 4'b0000;

This problem is fixed in the latest 4.1i Service Pack, available at:
http://support.xilinx.com/support/techsup/sw_updates
The first service pack containing the fix is 4.1i Service Pack 2.
AR# 12789
Date Created 10/08/2001
Last Updated 08/11/2003
Status Archive
Type General Article