AR# 12805: 6.1i - Does Xilinx support equivalency checking for RTL-to-RTL, RTL-to-Gate, or Gate-to-Gate?
AR# 12805
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6.1i - Does Xilinx support equivalency checking for RTL-to-RTL, RTL-to-Gate, or Gate-to-Gate?
Description
Keywords: RTL, gate, 4.1i, 5.1i, RTL, Equivalency
Urgency: Standard
General Description: Does Xilinx support equivalency checking for RTL-to-RTL, RTL-to-Gate, or Gate-to-Gate?
Solution
1
Xilinx supports only RTL-to-Gate equivalency checking. (For RTL-to-RTL and Gate-to-Gate checking, please contact the formal verification tool vendors.)
Xilinx supports formal verification tools so that equivalency checking is available for RTL-to-post synthesis and RTL-to-Layout designs that are targeted to Xilinx devices. Xilinx has neither validated nor endorsed the use of these tools for any other purposes (such as re-targeting, etc.). Xilinx recommends that you directly contact your formal verification tool vendors for further information regarding re-targeting and any other applications.
2
For related PrimeTime information, please see the following Answer Records: