UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 12829

12.1 Timing Closure/Timing Analyzer - How do I ensure that my design meets timing requirements/optimize for speed? (Timing tips)

Description

My design is not meeting timing requirements. Are there any tips available that will help me to improve the efficiency of my design?

Solution

The following are some tips to help you meet timing for your design. These suggestions assume you are already using the latest Xilinx design tools and service pack.

1. Ensure that you have set all applicable speed-related options in your synthesis tool and implementation tool. For example, you can generally specify that you prefer a fast design over one that uses less silicon. You can search within the help files of your synthesis tool and examine all the options for NGDBuild, MAP, and PAR.

In addition, running the tools from the command line sometimes offers you access to implementation options not available from the GUI. (For example, type "ngdbuild" at a DOS or UNIX prompt to list all available options.)

2. Critically evaluate your code and ensure that it is as tight as possible.

3. Evaluate your constraints to ensure that each one is both reasonable and necessary. Can you identify any false paths or multicycle paths in your design that will allow sections of the design to be treated more loosely by the tools?

4. Increase your PAR effort level to HIGH, so that more time will be spent on optimizing algorithms.

5. If you are within 5-10% of meeting timing requirements, try multipass PAR (MPPR).

6. If you are then within 1%, try re-entrant routing.

7. If you still cannot meet timing, you should consider:

- A more powerful synthesis tool

- A faster part (higher speed grade)

- A larger part (e.g., moving from XCV600E to XCV812E, then adjusting the amount of pipelining and parallelism)

For more details on timing constraints, please see the Timing Constraints User Guide: http://www.xilinx.com/support/documentation/sw_manuals/xilinx12_1/ug612.pdf

AR# 12829
Date Created 08/29/2007
Last Updated 12/15/2012
Status Active
Type General Article