UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 12832

FPGA Express - "Warning: Latch inferred in design '***' read with 'hdlin_check_no_latch'." (HDL-307)

Description

Keywords: Synopsys, FPGA Express, HDL, synthesis, warning

Urgency: Standard

General Description:
When I synthesize an HDL-coded design with FPGA Express, the following warning (HDL-307) is reported:

"HDL-307: Warning: Latch inferred in design '***' read with 'hdlin_check_no_latch'."

How do I avoid this warning?

Solution

If there is a case statement or "if/else" in the code, and if all the possible conditions and states are not covered, a latch is being inferred. This causes the warning message.

- For a case statement, fill up all possible states by using "others" for VHDL or "default" for Verilog.

- For "if/else", ensure that there is an "else" for every "if" so that all cases will be caught.
AR# 12832
Date Created 10/09/2001
Last Updated 08/11/2003
Status Archive
Type General Article