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AR# 12832

FPGA Express - "Warning: Latch inferred in design '***' read with 'hdlin_check_no_latch'." (HDL-307)


Keywords: Synopsys, FPGA Express, HDL, synthesis, warning

Urgency: Standard

General Description:
When I synthesize an HDL-coded design with FPGA Express, the following warning (HDL-307) is reported:

"HDL-307: Warning: Latch inferred in design '***' read with 'hdlin_check_no_latch'."

How do I avoid this warning?


If there is a case statement or "if/else" in the code, and if all the possible conditions and states are not covered, a latch is being inferred. This causes the warning message.

- For a case statement, fill up all possible states by using "others" for VHDL or "default" for Verilog.

- For "if/else", ensure that there is an "else" for every "if" so that all cases will be caught.
AR# 12832
Date 08/11/2003
Status Archive
Type General Article