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AR# 12857

7.1i CPLDFit - "WARNING:Cpld:987 - An internal 3-state buffer has been detected"


Urgency: Low

General Description:

Xilinx CPLDs do not support internal 3-state busses (with the exception of the XC9500 5V family); however, errors do not occur in my designs that use internal 3-state busses. What is happening to these internal busses?


All Xilinx devices with internal 3-state busses will pull up a floating line. Consequently, if both BUFEs are "0s" (when the enable line is a "1", the data goes through the buffer, and a "0" is hi-Z), then TBUS will be floating and pulled up to a "1". As a result, there is never a true floating condition on TBUS, regardless of whether the pull-up is attached.

3-state bus in design
3-state bus in design

The following is logically equivalent:

3-state bus in combinatorial logic
3-state bus in combinatorial logic

You can see that this is logically equivalent to the 3-state bus (with a pull-up). If there are three BUFEs on the TBUS line, you can simply add another OR2 parallel to the others.

The Xilinx CPLD Fitter does this in order to emulate the internal 3-state bus.

AR# 12857
Date 12/15/2012
Status Active
Type General Article