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AR# 12874

4.1i ABEL XST - The ABEL ".pin" delay function is not correctly implemented



Urgency: Standard

General description:
The ".pin" extension in the ABEL language may be used to create additional delay between an output and another signal that uses the output. The ".pin" extension implies the desire for pin feedback from the given output.

For example:
out2 = out1.pin

When a CPLD design is implemented in ISE 4.1i using the ABEL HDL language and ABEL XST (VHDL) or ABEL XST (VERILOG) synthesis tool, the ".pin" extension is optimized for functional equivalence and fastest timing.

However, the resulting timing differences can cause existing designs that worked when using the ABEL2BLIF flow to not work when the ABEL XST flow is used.


It is not currently possible to implement a delay function by means of the ABEL ".pin" function in the ABEL XST flow.

A temporary work-around is to enable the ABEL2BLIF flow with in the ISE 4.1i software. This is done by setting the following environment variable:

AR# 12874
Date 08/06/2003
Status Archive
Type General Article
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