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AR# 12882

4.1i CORE Generator - C_ADDSUB_V3_0: "Warning: Constant bit select out of range."

Description

Keywords: CORE Generator, COREGen, XilinxCoreLib, simulator, VCS

Urgency: Standard

General Description:
When I compile a project, the following warnings are reported:

"Warning: invalid partselect of parameter (/tools/xilinx/4.1i_sp1/SunOS/verilog/src/XilinxCoreLib/C_ADDSUB_V3_0.v line 170)"
"Warning: Constant bit select out of range (/tools/xilinx/4.1i_sp1/SunOS/verilog/src/XilinxCoreLib/C_ADDSUB_V3_0.v line 474)"
"Warning: Constant bit select out of range (/tools/xilinx/4.1i_sp1/SunOS/verilog/src/XilinxCoreLib/C_ADDSUB_V3_0.v line 480)"

Solution

The warnings are harmless and can be ignored.

The model has been updated in C_ADDSUB_V5_0.v and will not produce the warning message.

However, the following cores still use C_ADDSUB_V3_0:

C_ACCUM_V3_0
C_COMPARE_V3_0
C_COUNTER_BINARY_V3_0
C_SER_ADD_SUB_V3_0
C_TWOS_COMP_V3_0
CIC_V1_0
DDS_V2_0
SQM_V2_0
SQM_V3_0
AR# 12882
Date Created 10/16/2001
Last Updated 10/09/2003
Status Archive
Type General Article