The sink side of a PL4 core does not operate at the speed listed in the Data Sheet, or requires that the PHASE_SHIFT setting be significantly different from the default 64 operation speed.
Why do the Rdat and RCtl input paths have the DELAY attribute turned on?
This problem is fixed in the 3.1 version of the core. All subsequent versions of the core contain this fix.
The Xilinx Implementation tools add the DELAY attribute to these LVDS inputs; this is not appropriate for the PL4 core.
To prevent this from occurring, follow these steps:
1. Add the following lines to your design.ucf file:
NET "RDat_P*" NODELAY;
NET "RCtl_P" NODELAY;
2. Run the implementation tools again.
For related information, please see (Xilinx Answer 11917).
In version 4.x of PL4, these attributes are added to the UCF.