General Description: Synplify 7.0 does not recognize an instantiated BUFGCE as a clock buffer; therefore, Synplify 7.0 will infer a BUFGP instead of an IBUFG for the PAD.
The BUFGP is a macro that will expand into an IBUFG + BUFGMUX (configured as BUFG), resulting in two BUFGMUXs.
Solution
1
VHDL Example:
BUFGMUX instantiation using Synplify:
library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_signed.all;
entity bufgmux_instantiate is port ( clk_pad : in std_logic; clk_debug_pad : in std_logic; normal_mode : in std_logic; a : in std_logic_vector(15 downto 0); b : in std_logic_vector(15 downto 0); p : out std_logic_vector(31 downto 0) );
attribute xc_padtype : string; attribute xc_padtype of clk_pad: signal is "IBUFG"; attribute xc_padtype of clk_debug_pad: signal is "IBUFG"; -- this attribute forces external clock pad signal to be of type IBUFG instead -- of BUFGP inferred by default by Synplify
end entity bufgmux_instantiate;
architecture structural of bufgmux_instantiate is
signal clk: std_logic;
component BUFGMUX port ( O : out std_logic; I0 : in std_logic; I1 : in std_logic; S : in std_logic ); end component;
begin U1: BUFGMUX port map( O => clk, I0 => clk_debug_pad, I1 => clk_pad, S => normal_mode);
-- other code process (clk) begin if rising_edge(clk) then p <= a * b; end if; end process;
end structural;
2
Verilog Example
BUFGMUX instantiation using Synplify:
module bufgmux_instantiate (clk_pad, clk_debug_pad, normal_mode, a, b, p);