What effect does the USELOWSKEWLINES constraint have on various device families?
The USELOWSKEWLINES constraint is honored by the Virtex, Virtex-E, Spartan-II, and Virtex-II device families.
For Virtex, Virtex-E, Spartan-II:
USELOWSKEWLINES causes PAR to put the clock net on the backbone routing resources. If this cannot be done, PAR issues an error.
USELOWSKEWLINES causes PAR to use a template to route nets in a particular way that reduces skew. If this cannot be done, PAR will not issue an error or warning.