We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 12992

4.1i Timing Analyzer/Trace (TRCE) - The SRL16_1 is not appearing in the correct time group


General Description:

The SRL16-1 has an inverted clock, but it is being placed into the rising time group instead of the falling timing group. How do I work around this?


To avoid this problem, remove the SRL16-1 from the time group with an EXCEPT constraint, then explicitly add it to the falling time group.

This problem is fixed in the latest 4.2i Service Pack, available at:

The first service pack containing the fix is 4.2i Service Pack 1.

AR# 12992
Date 01/18/2010
Status Archive
Type General Article
Page Bookmarked