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AR# 13036

4.1i CORE Generator - My "mult_gen_v4_0" will not infer a MULT18X18S for input widths of 18 or smaller.


Keywords: CORE Generator, COREGen, mult_gen, pipeline, multiplier, MULT18X18, 18, 19, MULT18X18S

Urgency: Standard

General Description:
My "mult_gen_v4_0" will not infer a MULT18X18S for input widths of 18 or smaller. (Pipelined multipliers with less than 19 bit inputs should still use MULT18X18s.)


A bug in the CORE Generator Multiplier v4_0 code leads to a MULT18X18S being generated only if the multiplier contains more than one block multiplier. This is being fixed for the next release, which is v5_0.

With v4_0, the MULT18X18S will only appear if:

1. Maximum Pipelining is enabled and there is no ACLR port requested (as the block multiplier does not have an ACLR pin);
2. The "c_sync_enable" parameter is set to 0, (sclr_overrides_ce). This is just the way that the underlying block multipliers work;
3. The core has either an A or a B input width that is larger than 19 signed bits;
4. The Virtex-II multiplier block is selected.
AR# 13036
Date 10/09/2003
Status Archive
Type General Article
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