General Description: When CORE Generator is used to generate a core that has been previously captured by the IP Capture Tool, the RTL files may are not copied to my project directory. (This problem occurs only on PC platforms.)
If the RTL source files were bundled in with your design using the IP Capture Tool, and were extracted onto your Xilinx installation, then the RTL files should be located in following directory:
where: short_company_name = the string you entered for Short Company Name in the IP Capture session. corename = the Internal Module Name and the version number entered during the IP Capture session. architecture = the device family (e.g., Virtex, Virtex-II).
The work-around is to manually copy the RTL files from the directory above to your working project directory.