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AR# 13056

2.1 System Generator for DSP - Known Issues List

Description

Keywords: SysGen, MATLAB, Simulink, errata, KI

Urgency: Standard

General Description:
This Answer Record contains a list of Known Issues for System Generator v2.1.

Solution

1. Synplify Pro 7.0 is changing my register behavior (FDSE to an FD), which causes simulation mismatches.
Please see (Xilinx Answer 12953)

2. My masked subsystem leaves unused optional ports disconnected, causing simulation or implementation problems.
Please see (Xilinx Answer 13233)

3. My System Generator design contains a Sine/Cosine block; MAP reports an error similar to the following:
"ERROR:Pack:679 - Unable to obey design constraints."
Please see (Xilinx Answer 12596)

4. When does the multiplier block utilize embedded Virtex-II multipliers (MULT18x18S)?
Please see (Xilinx Answer 13112)
AR# 13056
Date Created 10/31/2001
Last Updated 06/22/2004
Status Archive
Type General Article