UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 1306

VHDL synthesis : tristate multiplexer versus combinatorial multiplexer.

Description


A lot of VHDL synthesizers are able to infer both tristate multiplexer

and combinatorial multiplexer (built in look up table). The use of one style

versus the other could affect the results in terms of speed and/or density.



A frequent mistake is to use the CASE statement to built tri-state multiplexer

instead of using a simple when clause.

Solution


The following first example describes a tristate multiplexer :



library ieee;

use ieee.std_logic_1164.all;



entity tristate is

port ( busa, busb, busc, busd, buse, busf: in std_logic_vector (7 downto 0);

valide : in std_logic_vector (5 downto 0);

clk : in std_logic;

result : out std_logic_vector (7 downto 0) );

end tristate ;



architecture tri_mux of tristate is



signal tri_bus : std_logic_vector (7 downto 0);



begin



tri_bus <= busa when valide(0) = '1' else "ZZZZZZZZ" ;

tri_bus <= busb when valide(1) = '1' else "ZZZZZZZZ" ;

tri_bus <= busc when valide(2) = '1' else "ZZZZZZZZ" ;

tri_bus <= busd when valide(3) = '1' else "ZZZZZZZZ" ;

tri_bus <= buse when valide(4) = '1' else "ZZZZZZZZ" ;

tri_bus <= busf when valide(5) = '1' else "ZZZZZZZZ" ;



register_output:process(clk)

begin

if clk'event and clk ='1' then

result <= tri_bus;

end if;

end process;

end tri_mux;





The second example describes a combinatorial multiplexer with

a CASE statement.



library ieee;

use ieee.std_logic_1164.all;



entity tristate is

port ( busa, busb, busc, busd, buse, busf: in std_logic_vector (7 downto 0);

valide : in std_logic_vector (5 downto 0);

clk : in std_logic;

result : out std_logic_vector (7 downto 0) );

end tristate ;



architecture lut_mux of tristate is



signal lut_bus : std_logic_vector (7 downto 0);



begin

mux_lut:process(valide)

begin

case valide is

when "000001" => lut_bus <= busa ;

when "000010" => lut_bus <= busb ;

when "000100" => lut_bus <= busc ;

when "001000" => lut_bus <= busd ;

when "010000" => lut_bus <= buse ;

when "100000" => lut_bus <= busf ;

when others => lut_bus <= "ZZZZZZZZ";

end case ;

end process;



register_output:process(clk)

begin

if clk'event and clk ='1' then

result <= lut_bus;

end if;

end process;

end lut_mux;
AR# 1306
Date Created 08/31/2007
Last Updated 10/27/2011
Status Archive
Type General Article