General Description When I import a design from 3.1i CORE Generator, "port mismatch" or "unconnected ports" messages are reported.
Solution
In the 3.1i CORE Generator, the .veo file was generated with upper-case port names; however, in the 4.1i, 4.2i, and 5.1i versions, the .veo and wrapper files are generated with lower-case port names. For an existing 3.1i design with cores, if a core is re-generated in the 4.1i, 4.2i, or 5.1i versions, but the Verilog instantiation of the design file is not changed, a mismatch in port names occurs during behavioral simulation and implementation.
To work around this problem, update the design files (Verilog source code) or simulation testbench to use the new instantiation template, which will have the port names in written out in the correct case.
If you are performing Verilog behavioral simulation, the simulation tool may include a switch that automatically converts port names to upper-case characters.
For example:
In Verilog-XL: verilog -u
In ModelSim: vlog -u
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AR# 13062
Date
03/04/2008
Status
Archive
Type
General Article
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