For a testbench or testbench waveform, several simulations can be run, each with a different model. What are the uses of these different models?
Behavioral VHDL Model:
Simulates the RTL code (behavioral), which is useful for testing design functionality.
Simulates the post-synthesis model, which is useful for determining whether or not the synthesis tool extracted the correct functionality from the code.
Simulates the post-MAP model, which is useful for determining if the mapper created the correct logic from the netlist.
Post Place-and-Route Model:
Simulates the placed and routed design in the chip, otherwise known as timing simulation. This model contains the complete timing information of the design.