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AR# 13068

ISE - What are the uses of the different timing models (behavioral, post-translate, post-MAP, timing)?

Description

For a testbench or testbench waveform, several simulations can be run, each with a different model. What are the uses of these different models?

Solution

Behavioral VHDL Model: 

Simulates the RTL code (behavioral), which is useful for testing design functionality.  

 

Post-Translate Model: 

Simulates the post-synthesis model, which is useful for determining whether or not the synthesis tool extracted the correct functionality from the code. 

 

Post-MAP Model: 

Simulates the post-MAP model, which is useful for determining if the mapper created the correct logic from the netlist. 

 

Post Place-and-Route Model: 

Simulates the placed and routed design in the chip, otherwise known as timing simulation. This model contains the complete timing information of the design.

AR# 13068
Date Created 08/29/2007
Last Updated 05/14/2014
Status Archive
Type General Article