The TBUFs in all FPGA architectures may access only the horizontal longlines, and each longline has a limited number of TBUFs that can access it. The number of TBUFs that may access a horizontal longline for a given part is listed in the Data Book.
If PAR error 4kpl:7 is referencing TBUFs, then the problem is that you have exceeded the number of TBUFs that can drive a single longline.
Solution
The following design hint may or may not be practical for your design. Divide up your TBUFs into two of more groups, each group driving its own node/line. Then, mux the resulting lines together, and develop control logic to drive the select line of the mux.