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AR# 13126

LogiCORE Dual Port Block Memory - When using asymmetric ports, the Dual-Port Block Memory Core requires more block RAM primitives than expected


When I generate a Dual-Port Block Memory Core using CORE Generator, more block RAM are required than expected. Why?

For example:

I am generating a Dual-Port Block Memory Core with the following settings:

Port A:

Width: 18

Depth: 2048

Configuration: Write Only

Port B:

Width: 36

Depth: 1024

Configuration: Read Only

Enable Pin

NOTE: Port A and Port B are asymmetric, meaning that different port width sizes exist.

A possible configuration is described (if each Virtex-II block RAM is in dual-port mode) in the Virtex-II Platform FPGAs: Complete Data Sheet, Table 15 - "Dual-Port Mode Configuration," page 22:

Navigate to: FPGA Device Families -> Virtex-II -> Virtex-II Complete Data Sheet (All four modules)

According to this table, only two block RAM are required:

- 1st BlockRAM:

Port A: 2048 x 9

Port B: 1024 x 18

- 2nd BlockRAM:

Port A: 2048 x 9

Port B: 1024 x 18

However, CORE Generator requires three blockRAM:

- 1st BlockRAM = RAMB16_S9_S18:

Port A is 2048 x 8

Port B is 1024 x 16

- 2nd BlockRAM = RAMB16_S9_S18:

Port A is 2048 x 8

Port B is 1024 x 16

- 3rd BlockRAM = RAMB16_S2_S4:

Port A is 8192 x 2 (only 2048 x 2 used)

Port B is 4096 x 4 (only 1024 x 4 used)


This occurs because the algorithm used to implement symmetric and asymmetric cores is slightly different. If the memory is symmetric, the algorithm uses the parity bits in the block memory. If the memory is asymmetric, the algorithm does not use the parity bits in the block memory. This is because the parity bits complicate the implementation of a generic algorithm for asymmetric ports.

So, if asymmetric ports are used, the algorithm does not use the parity bits for the primitives. This results in a RAMB16_S9_S18 primitive, effectively becoming a primitive; where Port A is 2048 x 8 and Port B is 1024 x 16. As this is the case, a third block RAM is needed to create the given memory.

There is no plan to change the algorithm of Dual Port Block memory core; however, all the engineering effort will be focused on improving the new Block Memory Generator Core. The new core already has the improved algorithm.

Selectable Memory Algorithm

The Block Memory Generator Core arranges block RAM primitives according to one of two algorithms: the minimum area algorithm and the selectable primitive algorithm. With the minimum area algorithm, it will optimize for the minimum block RAM usage, and when it is possible for the parity bits to be used, the core will use them.

AR# 13126
Date 12/15/2012
Status Active
Type General Article