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AR# 13131

MicroBlaze (MDK) - As PlatGen does not yet support the "-l verilog" option, how can I use MicroBlaze in my Verilog design?

Description

Keywords: MicroBlaze, Verilog

Urgency: Standard

General Description:
As PlatGen does not yet support the "-l verilog" option, how can I use MicroBlaze in my Verilog design?

Solution

1

Example wrapper file:

1. Run PlatGen without the "-flat" option to produce a top-level VHDL file.

2. Synthesize that top-level VHDL file, but disable I/O insertion in the synthesis tool -- this creates an EDIF file for the MicroBlaze system.

3. Create a wrapper file in Verilog that describes the input and output ports of the MicroBlaze system you just synthesized.

4. Instantiate that wrapper file in your top-level Verilog design.

The following example for is for Synplify:

In the MicroBlaze system top-level VHDL file:

entity system1 is
port (
-- instance GLOBAL
DEACTIVATE_N : out std_logic;
sys_reset : in std_logic;
sys_clk : in std_logic;
ENABLE_N : out std_logic;

-- instance uart_0
rx : in std_logic;
tx : out std_logic);
end system1;

Verilog wrapper for the EDIF file created from the above VHDL file:

module system1 (DEACTIVATE_N,
sys_reset,
sys_clk,
ENABLE_N,
rx,
tx); //synthesis syn_black_box

input sys_clk;
input sys_reset;
output tx;
input rx;
output DEACTIVATE_N;
output ENABLE_N;

endmodule

Top-level Verilog system (with instantiated MicroBlaze system) and a clock divider:

module top_level (clk, rst, tx, rx, enable);

input clk;
input rst;
output tx;
input rx;
input enable;

//top level module adds a clock enable and divider

reg [1:0]count;


always @ (posedge clk)
begin
if (rst)
count = 2'b00;
else if (enable)
count = count + 1'b1;
end

system1 my_system1(
.DEACTIVATE_N(),
.sys_reset(rst),
.sys_clk(count[1]),
.ENABLE_N(),
.rx(rx),
.tx(tx)
);
endmodule

2

(NOTE: As the EDK now supports Verilog, this solution is for MDK systems only.)

1. Run PlatGen with the "-flat" and "-i" options to produce a top-level netlist without I/O inserted.

2. Create a wrapper file in Verilog that describes the input and output ports of the MicroBlaze system you just synthesized.

3. Instantiate that wrapper file in your top-level Verilog design.
AR# 13131
Date Created 11/08/2001
Last Updated 04/23/2007
Status Archive
Type General Article