When I try to use the Verilog model for an asynchronous FIFO v5.0, I encounter the following problems:
- When the clocks are in phase (synchronous), I cannot read anything on "Dout".
- When using NC-Sim for behavioral simulation, the output of the FIFO is undefined prior to reading the FIFO.
If you observe the first problem above, shift the clocks in your testbench so they are not in phase, or use the synchronous FIFO model.
If you observe the second problem above, perform one of the following:
- Gate-level simulation, see (Xilinx Answer 8065)
- Timing simulation
- Ignore it; in hardware, the FIFO will actually output all 0's before performing a read
This problem is addressed in Async FIFO v5.1 Verilog model.