General Description: Functional Simulation and Hardware works, but in Timing Simulation, I see "?" on waveform output(s). Tracing the origin of the unknown value back, I found that an input to a component is unknown, while the output of the component that is driving the input is at a known value.
This problem can stem from the "time_sim" netlist file created by Synopsys' FPGA Express. Synopsys is writing out an EDIF netlist with matching names except for case.
For example, two nets, N115 and n115, are legal for implementation tools because they are case sensitive; however, the Aldec simulator and ModelSim cannot distinguish between these two nets because these tools are not case-sensitive.
To work around the warnings and unknown values, edit the time_sim.edn file and rename one of the two nets that are duplicated.